About Sentinely
Sentinely builds training and evaluation environments for AI that debugs chips, starting with clock-domain-crossing bugs.
Why this problem
When two parts of a chip run on different clocks, a signal passing between them can be lost, duplicated or corrupted, depending on timing. Ordinary RTL simulation gives every two-flop synchronizer the same fixed latency, so it can't see the bugs that depend on a flip-flop settling late. A grader built on it can give full reward to a fix that only works when timing cooperates, and reinforcement learning optimizes the reward it's given. We build a grader with a behavioral model of late settling, measure what it catches, and state what it doesn't model.
How we work
We report numbers as measured, with their scope: designs, seeds and clock ratios. We keep a log of each kind of patch that has fooled, or tried to fool, our grader.
Team
Sentinely is built by Sameer Abu Ghanima.